发明名称 |
Method to design and verify an integrated circuit device with multiple power domains |
摘要 |
A new method to design and verify a multi-power integrated circuit device is achieved. A multi-power gate-level netlist is provided. This multi-power gate-level netlist includes multi-power net information. This multi-power gate-level netlist is translated to thereby create a non-multi-power gate-level netlist. This translating comprises removing the multi-power net information. Circuit cells are then placed and routed to create a physical view of the multi-power integrated circuit device. This placing and routing step uses the non-multi-power gate-level netlist. Text labels for the multi-power net information are attached to the physical view. The physical view and the multi-power gate-level netlist are compared to verify the correctness of the physical view and to complete the design and verification of the multi-power integrated circuit device.
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申请公布号 |
US7103862(B2) |
申请公布日期 |
2006.09.05 |
申请号 |
US20040807037 |
申请日期 |
2004.03.23 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY |
发明人 |
SUNG NAI-YIN;HUANG HSING-CHIEN;TSAI JAN-HUN |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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