发明名称 Methods of plating via interconnects
摘要 Methods for filling high aspect ratio vias with conductive material. At least one high aspect ratio via is formed in the backside of a semiconductor substrate. The at least one via is closed at one end by a conductive element forming a conductive structure of the semiconductor substrate. The backside of the semiconductor substrate is exposed to an electroplating solution containing a conductive material in solution with the active surface semiconductor substrate isolated thereform. An electric potential is applied across the conductive element through the electroplating solution and a conductive contact pad in direct or indirect electrical communication with the conductive element at the closed end of the at least one via (or forming such conductive element) to cause conductive material to electrochemically deposit from the electroplating solution and fill the at least one via. Semiconductor devices and in-process semiconductor devices are also disclosed.
申请公布号 US7101792(B2) 申请公布日期 2006.09.05
申请号 US20030682703 申请日期 2003.10.09
申请人 MICRON TECHNOLOGY, INC. 发明人 KIRBY KYLE K.;FARNWORTH WARREN M.
分类号 H01L21/44;H01L21/288;H01L21/768;H01L23/48 主分类号 H01L21/44
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