发明名称 Method and apparatus for testing interconnect bridging faults in an FPGA
摘要 A bridging fault detection system allows for a high amount of test coverage using a low number of test configurations. The bridging fault detection system automatically creates optimal test configurations and test vectors without the need for precise layout information, and is adaptable to complex programmable device architectures. Testers can specify a precise level of testing coverage to optimize the testing processing. A programmable device with interconnect bias circuitry decreases the number of test configurations and thus the time needed to test for bridging faults. The interconnect bias circuit provides explicit test control over the unused lines in a configuration, driving them both high and low for complete test coverage between each line and all of its possible neighbors. The bridging fault detection system balances the available number of control test points against the number of interconnect segments stitched together by programmable connection to maximize the lines under test per configuration.
申请公布号 US7103813(B1) 申请公布日期 2006.09.05
申请号 US20030703400 申请日期 2003.11.06
申请人 ALTERA CORPORATION 发明人 TRACY PAUL;PANG ANTHONY;LEE ANDY;WRIGHT ADAM;SAINI RAHUL
分类号 G01R31/02;G06F11/267 主分类号 G01R31/02
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