发明名称 Optimizing depths of circuits for Boolean functions
摘要 Boolean circuits are designed with minimal depth by calculating the depth of an existing circuit. Those subtrees having a non-regular root cell (i.e., cells having other than one child or having a child of a type different from the cell) are balanced by constructing a new subtree. The cells are then iteratively transformed with parent and/or grandparent cells to reduce the depth of the circuit. The transformation may include balancing the subtree to make the parent cell the same type as the selected cell, or by creating a new cell as parent to the selected cell.
申请公布号 US7103868(B2) 申请公布日期 2006.09.05
申请号 US20020291982 申请日期 2002.11.12
申请人 LSI LOGIC CORPORATION 发明人 NIKITIN ANDREY A.;ANDREEV ALEXANDER E.
分类号 G06F17/50 主分类号 G06F17/50
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