Comparator circuit and method

摘要

A binary comparator circuit and a binary data comparison method for reducing a layout area and power consumption and/or increasing comparison speed. The binary data comparison circuit and method receive all N bits of each of a first binary data A_n-1A_n-2 . . . A₁A₀ and a second binary data B_n-1B_n-2 . . . B₁B₀, and compare the first binary data and the second binary data to determine which of the first binary data and the second binary data is larger according to the following equation: F(A<=B)=A_(n-1)'.B_(n-1)+(A_(n-1)'+B_(n-1)).{A_(n-2)'.B_(n-2)+(A_(n-2)'+B_(n-2)) . . . {A₁'.B₁+(A₁'+B₁).(A₀'+B₀)}} where subscripts denote a position of a bit of the N-bit binary data and a prime (') indicates that a bit is inverted, and outputting a signal corresponding to the comparison result.