| 摘要 |
981,720. Negative resistance logic circuits; STANDARD TELEPHONES & CABLES Ltd. Feb. 9, 1962 [Feb. 14, 1961], No. 5065/62. Heading H3T. A logic inverter comprises two circuit branches, each containing a negative and a positive resistance in series, one logic input signal switching both negative resistances to a low resistance state and the other logic signal switching one to switch to a high voltage state causing such an increase in current in the other as to switch it also to the high resistance state. The inverter stage comprising tunnel diodes 4 and 5 is controlled by a previous logical stage 8 which produces at 12 in response to a clock pulse at 13 a negative voltage (corresponding to a logical 0) or a substantially zero voltage (corresponding to logical " 1 ") depending upon which one of the tunnel diodes 9 and 10 is in the high resistance state. If a negative (" 0 ") output signal is produced at 12, diode 18 is non- conductive and a clock pulse from delay element 15 switches diode 4 to the low resistance state. As current drawn by this diode from a current source 25 is now relatively high diode 5 also switches to this state. Accordingly, the output voltage developed across diode 5 from the clock pulse is small and thus represents a logical (" 1 "). If, however, a logical " 1 " (zero voltage) had been present at 12, diode 18 would have been conductive and the clock pulse current would have caused diode 4 to switch to the high resistance state. The additional current now available from battery 25 causes diode 5 to switch to the high resistance state so that the resulting output voltage across diode 5 is a high value representing a logic " 0 ". The delay element 15 delays the clock pulse by an amount corresponding to the switching delay in circuit 8. In Fig. 2 (not shown) a further delay circuit is introduced between the circuit branches containing diodes 4 and 5 and an inductor is used as the current source 25, 26. Specification 922,580 is referred to. |
