发明名称 |
Register controlled delay locked loop with reduced delay locking time |
摘要 |
A register controlled delay locked loop includes a clock generation unit which receives an external clock signal for generating a source clock signal by buffering the external clock signal and for generating a delay monitoring clock signal and a reference clock signal by diving the source clock signal by a natural number; a delay line control unit which receives the reference clock signal and a feed-backed clock signal for generating a normal shift control signal and an acceleration shift control signal based on a result of a comparison between phases of the reference clock signal and the feed-backed clock signal; a delay line unit which receives the source clock signal for generating a delay locked clock signal by delaying the source clock signal according to a delay amount of the delay line unit determined by the normal shift control signal and the acceleration shift control signal; and a delay model unit for estimating a delay amount generated while the external clock signal is passed to a data output pin to generate the feed-backed clock signal, wherein an absolute delay amount based on the acceleration shift control signal is larger than that based on the normal shift control signal.
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申请公布号 |
US7098712(B2) |
申请公布日期 |
2006.08.29 |
申请号 |
US20040858976 |
申请日期 |
2004.06.01 |
申请人 |
HYNIX SEMICONDUCTOR, INC. |
发明人 |
LEE JAE-JIN |
分类号 |
H03L7/00;H03L7/081;G11C8/00;G11C8/04;G11C11/407;H03L7/06;H03L7/093 |
主分类号 |
H03L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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