发明名称 |
Source synchronous timing extraction, cyclization and sampling |
摘要 |
A translator tool for translating simulation test data generated to test clock recovery circuitry of a device from an event-based format to a cycle-based format readable by integrated circuit testers is presented. The simulation test data includes test timing irregularities intentionally injected into a serial data signal that will be processed by the clock recovery circuitry of the device under test. The translator tool includes a normalization function that extracts the intentionally injected timing irregularities from the event-based test data and generates corresponding normalized event-based test data without the extracted timing irregularities. The translator tool includes a cyclization engine that cyclizes the normalized event-based test data to generate corresponding cycle-based test data without the timing irregularities. Preferably, the extracted timing irregularities are stored and formatted into a timing irregularities file readable by the integrated circuit tester to allow the tester to reinject the timing irregularities back into the cycle-based test data using its own timing irregularities injection tools.
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申请公布号 |
US7100132(B2) |
申请公布日期 |
2006.08.29 |
申请号 |
US20040790960 |
申请日期 |
2004.03.01 |
申请人 |
AGILENT TECHNOLOGIES, INC. |
发明人 |
HILDEBRANT ANDREW S.;DOWDING DAVID |
分类号 |
G01R31/28;G06F17/50;G01R31/317;G01R31/3177;G01R31/3183;G06F9/45;G06F11/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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