Semiconductor device, receiver circuit, and frequency multiplier circuit

摘要

A delay circuit is provided including: 2n (n is a natural number) unit delay circuits for delaying an input clock signal (with the period of T) in accordance with a delay setting signal and generating and outputting 2n phases of delayed clock signals; a phase locked circuit for locking phases of the input clock signal and an output clock signal of a predetermined one of the unit delay circuits so as to be in phase and for outputting the delay amount setting signal for causing each of the first to the last stages of the unit delay circuits to delay the phase of an output clock signal by T/2n; and a correction circuit to which the input clock signal and the delay amount setting signal are input for generating a corrected clock signal by delaying the input clock signal and outputting it to the delay circuit.