发明名称 |
Electrical interconnect with minimal parasitic capacitance |
摘要 |
The invention discloses an electrical interconnect with minimal parasitic capacitance. In one embodiment, an apparatus comprises a semiconductor substrate, and first and second support structures formed on the substrate, where the second support structure at least partially surrounds the first support structure on the substrate. The first and second support structures are each configured to support an electrical connector to be formed over the first and second support structures on the substrate.
|
申请公布号 |
US7098540(B1) |
申请公布日期 |
2006.08.29 |
申请号 |
US20030729389 |
申请日期 |
2003.12.04 |
申请人 |
NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
MOHAN JITENDRA;NGUYEN LUU;SEGERVALL ALAN;GEE STEPHEN |
分类号 |
H01L23/48;H01L23/52;H01L29/40 |
主分类号 |
H01L23/48 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|