发明名称 Design system of alignment marks for semiconductor manufacture
摘要 A design system of an alignment mark for manufacturing a semiconductor device includes a memory which stores at least mark data including pattern information regarding plural kinds of marks and process data including condition information of manufacturing processes, and a first process simulator which simulates a substrate structure before patterning based on the process data, the substrate structure being formed in an identified manufacturing process. Moreover, the design system includes a second process simulator which simulates a processed shape of an identified mark after the patterning based on the simulated substrate structure and the process data, the mark formed in the manufacturing process, a signal waveform simulator which simulates a detection signal waveform of the mark, the waveform being obtained from the simulated processed shape of the mark, and a signal evaluation device which evaluates a suitability of the mark for the identified manufacturing process based on the simulated detection signal waveform.
申请公布号 US7100146(B2) 申请公布日期 2006.08.29
申请号 US20030636577 申请日期 2003.08.08
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 SATO TAKASHI;KOUNO TAKUYA;SAKAMOTO TAKASHI;SHIOYAMA YOSHIYUKI;HIGASHIKI TATSUHIKO;MORI ICHIRO;YOKOYA NOBORU
分类号 G03F1/08;G06F17/50;G01B9/02;G03F1/42;G03F9/00;H01L21/027;H01L21/82 主分类号 G03F1/08
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