Delay locked loop device

摘要

An apparatus for detecting locking information of a DLL clock in a semiconductor memory device includes a delayed locked loop for generating a first comparison signal and a first delay end signal; a phase state storing block for receiving the first comparison signal and the first delay end signal to thereby generate a locking selection signal; and a locking information detector for generating a locking state signal presenting the locking information in response to the first comparison signal, the first delay end signal and the locking selection signal.