发明名称 Instruction dependent clock scheme
摘要 A method and apparatus including a first circuit configured to receive multiple instructions including a first instruction having a first execution time, and to generate a first signal having a state dependent on the first execution time; a second circuit configured to receive the first signal and to generate a clock signal including a clock cycle having a period dependent on the state of the first signal; and a third circuit configured to receive the clock signal and execute a portion of the first instruction during the clock cycle, the first execution time corresponding to the portion of the first instruction.
申请公布号 USRE39252(E1) 申请公布日期 2006.08.29
申请号 US20020326169 申请日期 2002.12.23
申请人 INTEL CORPORATION 发明人 DALVI VISHRAM P.
分类号 G06F1/04;G06F9/38 主分类号 G06F1/04
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