| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a DLL circuit adjustment system that can adjust sampling timing of a DLL circuit without the increase of interface signals, an increase in encoding overhead quantity, and a decrease in data transfer efficiency. <P>SOLUTION: On a transmission side 1, an ECC generation section 5 outputs transmitted data 3 together with an added ECC code and data bits corresponding to adjusted DLL circuits of respective output channels of the ECC generation section 5 are transmitted to a reception side 2 instead of a pattern for sampling timing adjustment by using an adjustment channel selecting circuit 8 and a selector 11. On the reception side 2, the data bits are received through DLL circuits 12 provided correspondingly to respective channels of the received data and respective outputs of those DLL circuits are error-corrected by an error correcting detection section 6 to obtain received data 4. Consequently, normal data transfer can be performed while the DLL circuits 12 are timing-adjusted one by one. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
