发明名称 Pattern layout of word line transfer transistors in NAND flash memory which executes subblock erase
摘要 A semiconductor device includes a memory cell array, first and second selection circuits, and transfer transistors. The first selection circuit selects a block in the memory cell array. The second selection circuit selects several memory cells in the block to erase the memory cells corresponding to word lines in the block. The transfer transistors act as switches that selectively connect, of the word lines and driving lines, word lines and corresponding driving lines for each block. When the word lines are divided into word lines connected to memory cells to be erased and those connected to memory cells not to be erased, the number of transfer transistors connected to the word lines connected to the memory cells to be erased and arranged on both and opposite sides of a transfer transistor of a word line connected to a memory cell not to be erased becomes two or less.
申请公布号 US2006187737(A1) 申请公布日期 2006.08.24
申请号 US20060407146 申请日期 2006.04.20
申请人 发明人 FUTATSUYAMA TAKUYA
分类号 G11C8/00;G11C16/02;G11C16/04;G11C16/06;G11C16/16;H01L21/8247;H01L27/115;H01L29/788;H01L29/792 主分类号 G11C8/00
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