发明名称 Error correction circuit for dynamic RAM system, has read tree to receive data from data memory and parity data from parity memory, and also configured to produce display, whether error is occurred in data during storage within data memory
摘要 <p>The circuit has a data memory (52) to receive and store a data, and a write tree (56) to receive the data and produce a parity data. A parity memory (54) receives and holds the parity data. A read tree (58) receives the data from the data memory and thee parity data from the parity memory. The read tree also produces a display, whether an error is occurred in the data during storage within the data memory. Independent claims are also included for the following: (1) an application housing with an application chip and a evidently good chip (2) a memory device with a data memory (3) a method for detecting an error in a memory device (4) a method for manufacturing an application housing (5) a error correction method.</p>
申请公布号 DE102006007326(A1) 申请公布日期 2006.08.24
申请号 DE20061007326 申请日期 2006.02.16
申请人 INFINEON TECHNOLOGIES AG 发明人 BOWYER, STEPHEN;DANIEL, ALAN
分类号 G11C29/52;G06F11/08;G06F11/10 主分类号 G11C29/52
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