<p>An ESD protection system for I/O cells of an integrated circuit. The I/O cells of a bank of cells (201) include a first type of I/O cells (211) having ESD trigger circuits and a second type of I/O cells (213) having ESD clamp devices (241). In one embodiment, the ESD trigger circuits of the first type are located at the same area of an active circuitry floor plan as the area in the floor plan for the ESD clamp devices of the I/O cells of the second type.</p>
申请公布号
WO2006088543(A2)
申请公布日期
2006.08.24
申请号
WO2005US45203
申请日期
2005.12.14
申请人
FREESCALE SEMICONDUCTOR, INC.;MILLER, JAMES, W.;KHAZHINSKY, MICHAEL, G.;STOCKINGER, MICHAEL;WELDON, JAMES, C.
发明人
MILLER, JAMES, W.;KHAZHINSKY, MICHAEL, G.;STOCKINGER, MICHAEL;WELDON, JAMES, C.