| 摘要 |
In the cache circuit, an instruction cache hit counter counts the number of cache hits, and an instruction memory access counter counts the number of times of instruction access. An instruction cache hit rate computation/entry disabling control circuit computes the ratio of the cache hit count to the instruction access count (cache hit rate). If the cache hit rate exceeds an instruction cache entry disabling threshold, an instruction cache control circuit disables contents of instruction cache memory.
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