A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system interface to cache coherent memory and a low latency memory interface to a non-cache coherent memory. The system interface directs memory access for ordinary load/store instructions executed by the processor to the cache coherent memory. The low latency memory interface directs memory access for non-ordinary load/store instructions executed by the processor to the non-cache memory, thereby bypassing the cache coherent memory. The non-ordinary load/store instruction can be a coprocessor instruction. The memory can be a low-latency type memory. The processor can include a plurality of processor cores.
申请公布号
WO2006031462(A9)
申请公布日期
2006.08.24
申请号
WO2005US31295
申请日期
2005.09.01
申请人
CAVIUM NETWORKS;BOUCHARD, GREGG, A.;CARLSON, DAVID, A.;KESSLER, RICHARD, E.;HUSSAIN, MUHAMMAD, R.
发明人
BOUCHARD, GREGG, A.;CARLSON, DAVID, A.;KESSLER, RICHARD, E.;HUSSAIN, MUHAMMAD, R.