| 摘要 |
An integrated semiconductor memory ( 100 ) comprises a controllable voltage generator ( 30 ) for precharging bit lines (BL) of a memory cell array ( 10 ) to a precharge voltage (VEQ). During the read-out of a first and second memory state of memory cells (SZ) which are connected to the bit lines, a first and second signal swing (DeltaUH, DeltaUL) occurs on the bit lines, as a result of which the bit lines are charged to a first and a second voltage potential (V 1 , V 2 ). For the purpose of precharging the bit lines to the precharge voltage (VEQ), a first equalize current (I 1 ) and a second equalize current (I 2 ) are fed onto the bit lines by the controllable voltage generator ( 30 ), the current intensity of said currents in each case being measured by a detector circuit ( 60 ). A control circuit ( 20 ) alters the precharge voltage (VEQ) until the first and second equalize currents (I 1 , I 2 ) have identical magnitudes. The precharge voltage is then centered with respect to the first and second voltage potentials (V 1 , V 2 ).
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