| 摘要 |
<P>PROBLEM TO BE SOLVED: To solve the problem that, in the case of generating 2M multiple phase clock of frequency Fout by use of VCO (M stage ring oscillator) of a PLL circuit, it is necessary to oscillate VCO in the frequency Fout so that the delay time of one step of the ring oscillator may become Td=1/(2M×Fout); the higher the frequency of a desired multiple phase clock becomes, and the larger an output number also becomes, the smaller the value of Td becomes; and therefore the design becomes too difficult to obtain a stable performance in a required frequency range, so that the phase resolution capability may be reduced by the limit of the device ability. <P>SOLUTION: On a control voltage Vctrl at the time of locking a PLL circuit 110, the delay control of delay signal generation circuits 111 and 112 is carried out by arranging the generation circuits in two or more rows so as to multiplex them. Consequently, a multiple phase clock of high frequency can be generated without raising the capability of delay elements 102 and 107, as well as without reducing the phase resolution capability. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
