发明名称 DECODING METHOD AND DECODING DEVICE, AND PROGRAM THEREFOR
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a decoding method and a decoding device, and a program therefor that can reduce power consumption accompanied by decoding processing. <P>SOLUTION: A clock control section 11 predicts the number of clocks needed for processing from a variable modulation and demodulation section 13 to a deblocking filter 23 based upon header data etc., of encoded data. The frequency of a clock signal supplied from a clock control circuit 7 to a CPU 8 and a voltage supplied from a power source 6 to the CPU 8 are controlled based upon the prediction result. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p>
申请公布号 JP2006222648(A) 申请公布日期 2006.08.24
申请号 JP20050033209 申请日期 2005.02.09
申请人 SONY CORP 发明人 HIRANAKA DAISUKE
分类号 H04N19/00;H03M7/30;H04N19/127;H04N19/156;H04N19/44;H04N19/523;H04N19/625;H04N19/91 主分类号 H04N19/00
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