发明名称 |
Delay locked loop circuitry for clock delay adjustment |
摘要 |
A receiver adapted to be coupled to a data bus and configured to receive data in accordance with a receive clock includes first and second delay-locked loops. The first delay-locked loop is configured to generate a plurality of phase vectors from a first reference clock, and the second delay-locked loop is coupled to the first delay-locked loop and configured to generate the receive clock from at least one phase vector selected from the plurality of phase vectors and a second reference clock.
|
申请公布号 |
US2006188051(A1) |
申请公布日期 |
2006.08.24 |
申请号 |
US20060406557 |
申请日期 |
2006.04.18 |
申请人 |
|
发明人 |
DONNELLY KEVIN S.;CHAU PAK S.;HOROWITZ MARK A.;LEE THOMAS H.;JOHNSON MARK G.;LAU BENEDICT C.;YU LEUNG;GARLEPP BRUNO W.;CHAN YIU-FAI;KIM JUN;TRAN CHANH V.;STARK DONALD C.;NGUYEN NHAT M. |
分类号 |
H04L7/00 |
主分类号 |
H04L7/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|