| 摘要 |
A frequency divider circuit (108) for obtaining, from a plurality of first signals (ck0,ck60,ck120,ck180,ck240,ck300) having a first frequency (Fo) and being out-of-phase to each other, at least one second signal (Vd) having a second frequency (Fd) equal to a fraction of the first frequency. The frequency divider circuit includes a delaying block (F1,F2,F3) for each first signal, the delaying blocks being series-connected in a closed loop and having a signal input (D1,*D1; D2,*D2; D3,*D3), a signal output (Q1,*Q1; Q2,*Q2; Q3,*Q3) connected to the signal input of a next delaying block in the closed loop, and a clock input (C1,*C1; C2,*C2; C3,*C3) for receiving the corresponding first signal. Each second signal is taken from the signal output of a corresponding delaying block.
|
