发明名称 Clamp circuit for clamping a digital video signal
摘要 A clamp control circuit outputs a clamp control signal after a delay of a predetermined time if a digital video signal is detected. A sampling circuit that extracts sampling data of a pedestal level from a luminance corrected signal based on a clamp pulse at a timing of the back porch. A data averaging circuit calculates an average of the sampling data of the pedestal level. A data holding circuit holds a difference between the average and a digital signal processing reference level when the clamp control signal is output and also when the clamp control signal is not output. A level correction circuit corrects a level of the luminance signal based on the difference held by the data holding circuit and outputs the corrected luminance signal.
申请公布号 US7095452(B2) 申请公布日期 2006.08.22
申请号 US20030697332 申请日期 2003.10.31
申请人 RENESAS TECHNOLOGY CORP. 发明人 TACHIBANA MASANORI
分类号 H04N5/04;H04N5/16;H03G11/00;H03L5/00;H04N5/18;H04N5/57 主分类号 H04N5/04
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