发明名称 Gate electrode for FinFET device
摘要 In a method of forming a semiconductor device, a self-planarizing conductive layer is formed over a substrate that includes a topography having sharp drop-offs. The self-planarizing conductive layer is characterized by a substantially flatter surface than the underlying topography. As a result of the self-planarizing layer, a masking layer having a more uniform thickness may be formed over the conductive layer. Because the masking layer has a more uniform thickness, the masking layer may easily be patterned without causing damage to the underlying materials. These techniques may be used to fabricate, among other things, a FinFET without parasitic spacers formed around the fins and the source/drain regions.
申请公布号 US7094650(B2) 申请公布日期 2006.08.22
申请号 US20050039173 申请日期 2005.01.20
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 CHAUDHARY NIRMAL;SCHULZ THOMAS;XIONG WEIZE;HUFFMAN CRAIG
分类号 H01L21/336 主分类号 H01L21/336
代理机构 代理人
主权项
地址