| 摘要 |
Processes for packaging integrated circuits in microarray packages are described. In a method aspect of the invention, a first side of a metal sheet is etched to define a lead frame panel having a plurality of device areas. Each device area includes an array of contact posts suitable for forming contact pads and a plurality of lead traces. Each lead trace is coupled to an associated contact pad. The etching is arranged so that it does not etch all of the way through the metal sheet. Rather, the etching thins portions of the lead frame panel apart from the contact posts and lead traces to form a thin connecting sheet that holds the contact posts and lead traces in place. With this arrangement, the contact posts and lead traces defined in the resulting lead frame structure are held in place by the thin connecting sheet and are raised relative to the connecting sheet. The resulting etched leadframe panel is particularly well suited for use in microarray packages. In various embodiments, other lead frame structures may be incorporated into the device areas as desired.
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