Programming and erasing structure for a floating gate memory cell and method of making

摘要

A floating gate memory cell has a floating gate in which there are two adjacent floating gate layers. The top layer is made to have a contour while leaving the lower layer substantially unchanged. An interlevel dielectric and a control gate follow the contour of the floating gate to increase capacitance between the control gate and the floating gate. The two layers of the floating gate can be polysilicon in which the top layer has the contour formed therein by use of a sacrificial layer. The sacrificial layer is formed over the bottom polysilicon layer and etched. The top polysilicon layer is formed over the sacrificial layer. Subsequent processing of the top polysilicon layer exposes the remaining portion of the sacrificial layer so it can be removed; leaving the contour in the top polysilicon layer for the interlevel dielectric and the control gate.