| 摘要 |
A signal received under a multipath condition is buffered in storage memories 50 a and 50 b comprising two banks, and while overlap of write and read is allowed, the received data is supplied to matched filters 60 a and 60 b as much as possible, in a pipeline manner, and in-phase addition of four symbols per unit is performed in in-phase adders 80 a and 80 b. In the buffering in storage memories 50 a and 50 b, processor 40 adaptively changes the search period based on timing information acquired in advance.
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