| 摘要 |
A sampling circuit for testing an integrated circuit receives several signals from points of interest in the integrated circuit, digitizes them, and determines whether the digitized signal is above or below a threshold. By sampling the signal at different phases of a system clock signal, a determination can be made of when during the system clock signal the signal at a point of interest changed state. Circuits are provided for making minimal impact on the circuit being observed. Circuits are also provided for clocking the observed signal so that it can be compared to other observed signals.
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