发明名称 |
Dual damascene method for ultra low K dielectrics |
摘要 |
A method for forming a dual damascene opening to protect a low-K dielectric insulating layer including providing a semiconductor process wafer comprising a via opening extending though a thickness portion of at least one dielectric insulating layer; depositing a first dielectric layer stack layer comprising at least one dielectric insulating layer over the at least one dielectric insulating to seal the via opening; blanket depositing a second dielectric layer stack comprising at least one dielectric layer to form a hardmask over and contacting the first dielectric layer stack; photolithographically patterning and etching through a thickness of the hardmask and the first dielectric layer stack to form a trench opening etching pattern overlying and encompassing the via opening while leaving the via opening sealed; and, etching through a thickness portion of the at least one dielectric insulating layer to form a dual damascene opening.
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申请公布号 |
US7094683(B2) |
申请公布日期 |
2006.08.22 |
申请号 |
US20030633909 |
申请日期 |
2003.08.04 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
YEH CHEN-NAN;LU YUNG-CHENG |
分类号 |
H01L21/4763;H01L21/768 |
主分类号 |
H01L21/4763 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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