发明名称 Data processing system with bypass reorder buffer having non-bypassable locations and combined load/store arithmetic logic unit and processing method thereof
摘要 A data processing system for executing a plurality of instructions having a prescribed program order comprises a register file, a reorder buffer, and a plurality of functional units. The register file includes a plurality of registers to store data. The reorder buffer includes N buffer locations of which M buffer locations are bypassable and N-M buffer locations are non-bypassable, wherein N and M are integers and N>M. Each functional unit is capable of executing instructions regardless of the prescribed program order. The reorder buffer temporarily stores data corresponding to the plurality of instructions. When data of one of the plurality of instructions to be executed by a corresponding one of the plurality of functions units is temporarily stored in one of the M bypassable buffer locations, the reorder buffer transfers the data in one of the bypassable M buffer locations to the corresponding one of the functional units in order to execute the instruction. The register file also stores data corresponding to retired ones of the plurality of instructions.
申请公布号 US7096345(B1) 申请公布日期 2006.08.22
申请号 US20030672774 申请日期 2003.09.26
申请人 MARVELL INTERNATIONAL LTD. 发明人 CHEN HONG-YI HUBERT;LEE RICHARD YEN-CHING;YUNG GEOFFREY;TJENG JENSEN
分类号 G06F9/30 主分类号 G06F9/30
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