FEATURE FAILURE CORRELATION

摘要

Techniques are disclosed for determining the likelihood that a known feature in an integrated circuit design will cause a defect during the manufacturing process. According to some of these techniques, various logical units that incorporate an identified design feature are identified, and the amount that the design feature occurs in each of a plurality of these logical units is determined. The failure rate of integrated circuit portions corresponding to at least these logical units are then obtained. A feature failure coefficient indicating the likelihood that the feature will cause a defect then is determined by correlating the failure rates with the amount of occurrences of the feature. Some of these techniques additionally are used to identify new design features that are more likely to cause a defect. More particularly, the failure rates for logical units are predicted based upon the amount of the known features occurring in each of the logical units and their predicted impact upon the yield of portions of an integrated circuit corresponding to these logical units. These predicted failure rates are then compared with the actual failure rates of integrated circuit portions corresponding to the logical units, and the portions having the largest discrepancy are identified.