发明名称 |
Method and apparatus for implementing a combined data/coherency cache |
摘要 |
A method and apparatus for implementing a combined data/coherency cache for a shared memory multi-processor. The combined data/coherency cache includes a system cache with a number of entries. The method includes building a system cache directory with a number of entries equal to the number of entries of the system cache. The building includes designating a number of sub-entries for each entry which is determined by a number of sub-entries operable for performing system cache coherency functions. The building also includes providing a sub-entry logic designator for each entry, and mapping one of the sub-entries for each entry to the system cache via the sub-entry logic designator.
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申请公布号 |
US2006184744(A1) |
申请公布日期 |
2006.08.17 |
申请号 |
US20050056809 |
申请日期 |
2005.02.11 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
LANGSTON KEITH N.;MAK PAK-KIN;WAGAR BRUCE A. |
分类号 |
G06F13/28 |
主分类号 |
G06F13/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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