| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device where a pulse signal of a bit line selection signal CSL is securely supplied to a DQ gate, the skew of the bit line selection signal CSL in a sense amplifier bank is suppressed and a high speed reading/writing operation is realized. <P>SOLUTION: The DQ gate arranged between a pair of bit lines BL and /BL and a pair of data lines DQ and /DQ sets a part between a pair of bit lines and a pair of data lines to a connection state or an interruption state by the bit line selection signal LCSL. A CSL control circuit 13A controls the bit line selection signal LCSL supplied to the DQ gate. A redriver RD arranged between the CSL control circuit 13A and the DQ gate drives the bit line selection signal GCSL supplied from the CSL control circuit 13A, and outputs the signal LCSL to the DQ gate. The sense amplifier bank 12 is constituted of a sense amplifier, a pair of data lines and the DQ gate. The redriver RD is arranged in the sense amplifier bank 12. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
