发明名称 Thread priority method, apparatus, and computer program product for ensuring processing fairness in simultaneous multi-threading microprocessors
摘要 A method, apparatus, and computer program product are disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles. The clock cycle priority is assigned according to a standard selection definition during the standard selection state by selecting the first thread to be a primary thread and the second thread to be a secondary thread during the standard selection state. If a condition exists that requires overriding the standard selection definition, an override state is executed during which the standard selection definition is overridden by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.
申请公布号 US2006184946(A1) 申请公布日期 2006.08.17
申请号 US20050055850 申请日期 2005.02.11
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 BISHOP JAMES W.;LE HUNG Q.;NGUYEN DUNG Q.;SINHAROY BALARAM;THOMPTO BRIAN W.;YEUNG RAYMOND C.
分类号 G06F9/46 主分类号 G06F9/46
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