发明名称 |
Automatic reconfiguration of an I/O bus to correct for an error bit |
摘要 |
A test pattern is loaded into a driver data shift register and sent from a driver chip to a receive chip over an M bit bus (0 to M-1). The test pattern is also generated at the receiver chip and used to compare to the actual received data. Failed compares are stored as logic ones in a bit error register (BER). A counter determines the number of failures by counting logic ones from the BER. The contents of a error position counter are latched in a error position latch and used to load a logic one (at the error bit position) into daisy chained self-heal control registers (SCR) in the receiver chip and the driver chip. The SCR sets a logic one into all bit positions after the error bit isolating the failed bit path and adding a spare bit path which is in bit position M.
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申请公布号 |
US2006182187(A1) |
申请公布日期 |
2006.08.17 |
申请号 |
US20050055807 |
申请日期 |
2005.02.11 |
申请人 |
LIKOVICH ROBERT B JR;REESE ROBERT J;MENDENHALL JOSEPH D;BARKER KENNETH J |
发明人 |
LIKOVICH ROBERT B.JR.;REESE ROBERT J.;MENDENHALL JOSEPH D.;BARKER KENNETH J. |
分类号 |
H04B3/00 |
主分类号 |
H04B3/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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