| 摘要 |
A method for designing a semiconductor integrated circuit includes steps of (a) to (e). The step (a) is a step of placing a plurality of elements based on circuit data including data of the plurality of elements to be placed on a semiconductor integrated circuit. The step (b) is a step of estimating a position of an interconnection branching node at which an interconnection branches off to each of the plurality of elements. The step (c) is a step of estimating each interconnection length between the interconnection branching node and each of the plurality of elements. The step (d) is a step of calculating a delay timing variation based on the each interconnection length, wherein the delay timing variation is a variation of an arrival time when a signal travels from the interconnection branching node to each of the plurality of elements. The step (e) is a step of verifying whether the delay timing variation is within a design allowable range of the semiconductor integrated circuit.
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