| 摘要 |
A host controller ( 400 ) for interfacing one or more electronic devices ( 410, 411 ) to a packet-based timeshared bus, such as a system bus ( 402 ) or a universal serial bus ( 409 ), is disclosed. The host controller ( 400 ) comprises a first memory device ( 413 ) storing a sequence of predetermined transaction descriptors (TD) and a second memory device ( 405, 406 ) for storing payload data transmitted over a bus ( 402, 409 ). A transaction sequencer ( 407 ) is also provided that is operable cyclically to execute transactions defined by the transaction descriptors (TD) stored in the first memory device ( 413 ) so as to transmit or receive payload data in the second memory device ( 405, 406 ). By cycling through a predetermined set of transaction descriptors (TD) without the need to initially compile an operational set of transaction descriptors to process, the host controller ( 400 ) can operate as a simple slave device on a wide variety of existing buses. As an additional benefit, the host controller ( 400 ) does not require the use of bus mastering or direct memory (DMA) techniques, which leads to the provision of a simplified and inexpensive device.
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