| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a semiconductor memory which can hardly interfere with speeding up of operation even when the length of a bit line increases or arrangement pitches of bit line is reduced. <P>SOLUTION: The semiconductor integrated circuit device is equipped with; an even number bit line BLe; an odd-number bit line BLo; a cell source line CELSRC; a 1st memory component connected between the even number bit line BLe and the cell source line CELSRC; and a 2nd memory component connected between the odd-number bit line BLo and the cell source line CELSRC and belonging to the same column with the 1st memory component. When programming data to the 1st memory component, program data is given to the 1st memory component through the even number bit line BLe, and a potential suppressing a program is given to the 2nd memory component through the cell source line CELSRC in a state suspending the odd-number bit line BLo. When programming the data to the 2nd memory component, the reverse process is taken. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
