SPEECH COMPRESSION CODING PROCESSOR AND METHOD FOR STARTING SYNCHRONOUS COMPRESSION CODING USED THEREFOR

摘要

PROBLEM TO BE SOLVED: To provide a speech compression coding processor capable of offsetting synchronization deviation between an image baseband signal and a speech baseband signal.

SOLUTION: A bit embedding timing determination circuit 13 determines timing for embedding bits 102 for starting synchronous compression coding in a speech baseband signal 101 outputted from a speech baseband signal transmission system circuit 11, and determines at what timing of the input speech baseband signal 101 to make a speech compression system circuit 12 perform compression coding, and directs the timing to a bit superposition circuit 14. The bit superposition circuit 14 superposes the bits 102 for starting the synchronous compression coding on the speech baseband signal 101. The speech compression system circuit 12 is always monitoring the bits 102 for starting synchronous compression coding, and when the circuit finds the bits 102, it starts the coding process to the speech baseband signal 101.

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