发明名称 |
Post high voltage gate dielectric pattern plasma surface treatment |
摘要 |
The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.
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申请公布号 |
US2006183337(A1) |
申请公布日期 |
2006.08.17 |
申请号 |
US20060343680 |
申请日期 |
2006.01.31 |
申请人 |
KIRKPATRICK BRIAN K;KHAMANKAR RAJESH;BEVAN MALCOLM J;GURBA APRIL;ALSHAREEF HUSAM N;MONTGOMERY CLINTON L;SOMERVELL MARK H |
发明人 |
KIRKPATRICK BRIAN K.;KHAMANKAR RAJESH;BEVAN MALCOLM J.;GURBA APRIL;ALSHAREEF HUSAM N.;MONTGOMERY CLINTON L.;SOMERVELL MARK H. |
分类号 |
H01L21/302;B44C1/22;C23F1/00;H01L21/28;H01L21/311;H01L21/314;H01L21/8234;H01L21/8238;H01L29/51 |
主分类号 |
H01L21/302 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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