发明名称 Memory
摘要 A memory capable of suppressing reduction of data determination accuracy is provided. This memory comprises a memory cell connected to a bit line for holding data and a bipolar transistor whose base is connected to the bit line. In data reading, the memory reads the data by amplifying a current, corresponding to the data of the memory cell, appearing on the bit line with the bipolar transistor.
申请公布号 US2006181945(A1) 申请公布日期 2006.08.17
申请号 US20060353089 申请日期 2006.02.14
申请人 SANYO ELECTRIC CO., LTD 发明人 MURAYAMA YOSHIKI;YAMADA KOUICHI
分类号 G11C7/00 主分类号 G11C7/00
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