| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a serial mode setting circuit capable of facilitating timing designing by circuit refinement. <P>SOLUTION: Odd-number data among set data D[1] to D[N] are serially input to the data input terminal of the flip-flop F11 of the initial stage of a shift register operated by two-phase clocks SERCLK 1 and SERCLK 2, and shifted to be stored. Then, a setting signal SEREN which is another clock is set to a high level to transfer and store the odd-number data in flip-flops F21, F23, ..., F2[n-1]. Subsequently, even-number data are input and stored in the shift register, and then the SEREN is set to a low level to transfer and store the even-number data in flip-flops F22, F24, ..., F2n. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
