| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a shift register which prevents a transfer pulse from penetrating, and realizes low power consumption. <P>SOLUTION: A data transfer unit circuit Uaj includes first and second circuits. When a transfer direction is to the right, the first circuit functions as a writing means, and the second circuit functions as a storage means. The first circuit has a write switch, constituted of first and second transistors P1 and N1, and the second circuit has a holding switch, constituted of third and fourth transistors N2 and P2. The write and hold switches are operated by toggles. The clock control circuit Ubj generates first to fourth signals CK1j to CK4j so that the write and hold switches both become off during their state transition. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
