| 摘要 |
An input inverter section inverts a plurality of input signals to generate complementary signals and supplies signals complementary to these input signals to a logic circuit network. The logic circuit network comprises a plurality of pairs of depletion type NMOSs (NDMOSs) whose conducting states are respectively controlled on a complementary basis by the supplied signals. Since each of the NDMOSs has a threshold voltage set negative, a drain current flows even if its gate voltage is 0V, and hence it is not brought into a complete off state. It is therefore possible to speed up a change from an off state to an on state and raise a signal of an "H" level at a node from which a signal indicative of the result of logical operations is outputted, to a potential identical to a power supply potential. The signal at the node is outputted from an output buffer section as an output signal.
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