摘要 |
<p>The device has two synchronizing modules (MA, MB), respectively, including BITS/SSU/Line timing select modules (SM1A, SM1B) delivering intermediate clocks issued from inner or outer reference clocks. Clock generating modules (SM2A, SM2B) deliver main clocks issued from the intermediate clocks. Reference clock distributing modules (SM3A, SM3B) deliver output clocks issued from the main clocks. An independent claim is also included for an equipment for a synchronous transport network.</p> |