发明名称 Design and layout techniques for low parasitic capacitance in analog circuit applications
摘要 A semiconductor device that reduces the parasitic capacitance between a conductive trace and a substrate, and a method of fabricating the same. The semiconductor device includes a substrate, an insulator layer disposed upon the substrate, a conductive trace disposed upon the insulator layer, and an element disposed between the substrate and the conductive trace. A first capacitance exists between the conductive trace and the substrate and a second capacitance results between the conductive trace and the substrate due to the presence of the element. The second capacitance is in series with the first capacitance, thereby reducing an effective capacitance between the conductive trace and the substrate.
申请公布号 US7091617(B2) 申请公布日期 2006.08.15
申请号 US20050084784 申请日期 2005.03.21
申请人 BROADCOM CORPORATION 发明人 CHEN CHUN-YING
分类号 H01L29/76 主分类号 H01L29/76
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