| 摘要 |
Error correction and detection codes are designed with several properties: the ability to perform error correction and detection operations via syndrome generation in multiple cycles of information delivery from a source such as a set of memory chips; a code structure which is cooperatively designed in terms of the bits-per-chip architecture of a set of memory chips so as to provide enhanced robustness in the face of bus line and chip failures; and a structured parity check matrix which provides circuits which are cheaper, take up less room, and are faster than standard designs.
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