发明名称 Direct synthesis clock generation circuits and methods
摘要 A clock generator includes input circuitry for receiving an input signal and generating a memory address therefrom. A memory stores digital data indexed by the memory address which represents at least a portion of an analog clock. A digital to analog converter converts data retrieved from the memory to generate the analog clock which is then filtered by a filter and then converted into digital output clock.
申请公布号 US7092476(B1) 申请公布日期 2006.08.15
申请号 US20010010819 申请日期 2001.12.06
申请人 CIRRUS LOGIC, INC. 发明人 MELANSON JOHN LAWRENCE
分类号 H03D3/24 主分类号 H03D3/24
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